Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering
نویسندگان
چکیده
منابع مشابه
Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering
This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS...
متن کاملReduction of Power Dissipation in Logic Circuits
The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today’s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the long-term reliability of circuits...
متن کاملReduction of Power Dissipation in Logic Circuits
The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today‟s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the longterm reliability of circuits ...
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Logic Behavior of Double BJT BiCMOS device under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS, to bring out the testability differences.
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ژورنال
عنوان ژورنال: VLSI Design
سال: 2002
ISSN: 1065-514X,1563-5171
DOI: 10.1080/1065514021000012165